CPU & von Neumann architecture

Suppose you enter 7. To obtain 12, the computer needs more than the number 7: it also needs instructions telling it to read, add, and output. The von Neumann stored-program idea puts instructions and data in the same main memory. The CPU—the central processing unit—reads and executes those instructions.

Memory contains numbered locations. A location’s number is its address; the information stored there is its content. Asking for address 12 is like choosing a numbered drawer. It does not mean that the drawer must contain the number 12.

Information is represented by bits: each bit is a 0 or a 1. A bus is a set of connections carrying signals. An address bus identifies where to access; a data bus carries bits; control signals specify actions such as READ or WRITE. Instructions also travel as bits on the data bus. These colours distinguish signal roles, not three types of instruction.

It needs small places to keep information while it works. These are registers: fast storage locations inside the CPU. The program counter (PC) remembers the next instruction’s address. The instruction register (IR) keeps the instruction being executed. The control unit (CU) reads that instruction and directs the other parts. The arithmetic and logic unit (ALU) does the calculation.

First fetch an instruction from memory. Next decode it: identify the operation and any operand, the value or location it uses. Then execute it. Each of these phases can require several smaller transfers, shown below as micro-operations. Press Step to complete one transfer; Play follows the whole program.

Select a component: why does it need to exist?

The Blender model shows a functional cutaway, with extra space between parts so the signals can be followed. It is not the transistor layout of a particular commercial chip. This machine uses one accumulator, 12-bit words, a 4-bit address space, and explicit input/output instructions. Modern CPUs may arrange these functions very differently.

A bit has two possible values, 0 and 1. A word is a fixed-size group of bits; here it has 12. Our instruction uses its first four bits as the operation code, or opcode. The final eight bits contain an operand field. For ADD and STORE, the low four operand bits identify one of the 16 memory locations; the remaining four are zero.

For example, 0010 selects ADD; 00001100 represents 12. So 0010 00001100 means “add the value at address 12”. IR keeps these bits, and the control unit decodes them. ADD is the readable name of that code, not a word that the hardware understands as English.

The clock coordinates when stored values change. A program instruction is not necessarily one clock cycle: fetching, decoding, and execution can need several cycles. The animation slows transfers so you can inspect them; its seconds are not a CPU speed measurement.

Now that we can follow one instruction, imagine dividing its work between five stages. Once the first instruction leaves the fetch stage, that stage can begin fetching another instruction while the first is decoded elsewhere. This overlapping arrangement is a pipeline. It is an implementation technique, not a requirement of the von Neumann idea.

The next demonstration uses a separate five-stage machine with registers R1, R2, … rather than a single accumulator. Ri names storage location i in the register bank. Each row is an instruction, each column one clock cycle. The gold banks between stages are pipeline registers: they hold intermediate values, destination numbers, and control bits between clock edges.

Assume five stages of one cycle each, independent instructions, and no stalls. Completing four instructions separately takes 4 × 5 = 20 cycles. With overlap, the first takes 5 cycles, then one finishes in each of the next 3 cycles: 8 in total. For k instructions:

The first instruction still takes five cycles. What improves is throughput: how many instructions finish over time. Switch to the dependency example to see why real pipelines cannot always finish one instruction per cycle. A result that is not ready forces a wait unless another mechanism, such as forwarding, can safely supply it earlier.